This invention relates to the formation of masks useful in photolithography for the fabrication of semiconductor devices, and more particularly, to a construction of multiple-layer solid-state wafer by a development of masks on a wafer structure, during construction of the wafer, to allow for a succession of photolithographic steps including deposition of various materials to be performed sequentially at a work station followed by a succession of etching steps to be performed sequentially at a separate work station, thereby to reduce the number of times that a wafer need be transferred between work stations.
In the use of photolithography for the construction of semiconductor devices as well as other devices such as masks and reticles, the construction process involves numerous steps which include the exposure of photoresist through a mask to delineate specifically shaped areas which are to be etched. There are situations in which a plurality of exposure steps are to be performed sequentially with a plurality of masks to accomplish differing amounts of exposure of the various areas to be etched.
The manufacturing process can be simplified by reduction of the number of exposure steps by use of a gray level mask. A gray level mask allows a defining of two or more conventional mask levels in a single exposure step, and may be configured of various thickness of blocking materials for protection of underlying layers from various etchants used in a manufacturing process. This technique lends itself to process clustering with its potential for low defect density, and also facilitates manufacture by reducing the number of masking levels required. The technique also reduces tolerances which need be employed with various masking patterns. By way of example, an important use of gray level mask technology is for recessed multilevel wiring applications where via and interconnect wiring patterns may be produced by a reduced number of manufacturing steps.
One area of interest in the fabrication of gray-level masks is in the use of a layer of glass which has been fabricated to provide a desired level of opacity to the illuminating radiation of a photolithographic step employed in the manufacture of a semiconductor chip circuit. Fabrication of a layer of a glass material can be accomplished in accordance with the teaching of three United States Patents to Wu, namely, U.S. Pat. Nos. 4,894,303; 4,670,366; and 4,567,104 wherein there is an exchange of silver ion with the metal ions of alkali metal silicates and oxides employed in the glass to provide a desired amount of light transmissivity.
A problem arises with presently available gray level masks in that the masks are difficult to fabricate and, furthermore, produce inadequate image quality in many applications. By way of example in the fabrication of a gray level mask, it has been the practice to form the mask by an array of spaced-apart chromium islands in the nature of a half-tone screen wherein each chromium island is opaque to ultraviolet radiation while spaces between the islands allow passage of the radiation. The half-tone screen is constructed by use of electron-bream lithography so as to produce spaces between the islands wherein the spaces have dimensions smaller than a wavelength of the optical radiation. The islands may also have dimensions smaller than the wavelength of the optical radiation. As a result, there is a significant attenuation of the optical radiation transmitted through the mask. The resulting transmissivity of the mask is significantly more than that of a totally opaque mask region and significantly less than that of a totally transparent mask region. Thus, the resulting mask is a gray level mask, but a mask which produces a lower quality image than is desired. The amount of transmissivity is defined by the dimensions of the chromium islands and the spaces.
A further disadvantage of the foregoing gray level mask is the fact that images formed in the gray areas have sloped sidewalls which are unacceptable for use in producing semiconductor products requiring the higher resolution for condensed packaging of circuit elements as are being contemplated for the near future. With respect to other techniques which have been employed in the fabrication of gray level masks, there has been the disadvantage that the other fabrication methods require precise electron-beam dose control to make optical masks or electron-beam proximity correction, and produce gray layers of specific opacity.